Shallow trench isolation (STI) is an integrated circuit feature that prevents electrical current leakage between adjacent semiconductor device components. STI structures are commonly used in CMOS devices, and are typically formed early during the semiconductor device fabrication process, before transistors are formed. The key steps of a conventional STI process involve etching a pattern of trenches in a silicon substrate, depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches, and removing the excess dielectric using chemical-mechanical planarization (CMP).
However, the CMP processing involved in conventional STI formation may cause one or more related problems. For example, the CMP process may produce a significant center-to-edge bias that may result in sufficient variation across the wafer to cause yield fallout. As another example, CMP may cause localized non-uniformity and dishing of the field oxide. Further, the CMP process may leave oxide residue on the largest active areas, which may cause SiN residue that results in yield loss. Finally, the conventional STI formation processing using CMP involves a relatively large number of steps.